# GC1 Rev D engineering review — 7 September 2026

**Fabrication scope: a small engineering prototype batch. This is not a validated finished Geiger counter.** The PCB has been revised against the purchased website BOM and the supplied *PCB Layout Rules Checklist*, PCB-11 Rev A, by John Teel / Predictable Designs. Native ERC, DRC, netlist parity and independent geometry checks are included. They do not establish transistor switching behavior, safe firmware, tube fit, RF performance or enclosure suitability.

Open `GC1-RevD.kicad_pro` in KiCad 10 or newer. Keep the project, `.kicad_dru`, `fp-lib-table`, and `GC1_RevD.pretty` library together. Use the complete project ZIP. The fabrication ZIP contains the four copper layers and separate plated/unplated drills; do not order it as a two-layer PCB.

## Required changes to the purchased parts

| References | Action | Reason |
|---|---|---|
| Q1 | Replace MMBTA42LT1G with Nexperia PBHV8560ZX | The old 300 V transistor cannot withstand the approximately 400 V collector swing. New 600 V SOT223 footprint; base 1, collector 2 and tab, emitter 3. |
| RB1 | Replace 2.2 kΩ with 100 Ω, RC0603FR-07100RL | Approximately 24 mA nominal pulsed base drive; GPIO loading and turn-off need measurement. |
| RBE1 | Add 100 kΩ, RC0603FR-07100KL | Base-emitter pull-down while the GPIO is high impedance. |
| RPU1 / RPU2 | Add two 4.7 kΩ, RC0603FR-074K7L | Explicit SDA/SCL pull-ups to 3.3 V. |
| C2 / C3 | Keep CGA6M1C0G3A472G200AC | Corrected from 2220 to the actual 1210 land pattern. |
| L2 | Keep LQG15HS27NJ02D | Corrected from 0603 to 0402. |
| ESD1 | Keep TPD1E0B04DPYR | Replaced the generic diode lands with the DPY0002A land pattern. |
| MC1 / MC2 | Fit Littelfuse 01000058Z / Keystone 6049 solder-in contacts | Identical four-hole footprints accept either contact; JP1 underside links select the polarity. Catalogue dimensions inform the prototype pattern; actual tube fit and assembled insulation remain unqualified. |

The original purchasing CSV is preserved as `purchased-website-bom.csv`. `reviewed-bom.csv` and `replacement-parts.csv` identify the final parts and changes. New component prices and availability have not been asserted.

## Circuit findings

The C2/D1/D2 circuit is an AC-coupled peak rectifier, not a stage that doubles a 0–200 V switch waveform to 400 V. `simulation/pump-topology.cir` gives approximately 199.5 V for that imposed waveform. Q1 therefore needs to tolerate the full output voltage and overshoot. The replacement's 600 V rating and pinout come from the [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/PBHV8560Z.pdf). The tab is electrically live; do not attach it to a ground heatsink. Its standard-footprint thermal resistance is 190 K/W, so temperature rise and switching loss must be measured rather than inferred from its larger package.

The 30 MΩ + 68 kΩ feedback divider draws **13.303 µA and 5.321 mW at 400 V**. The former website's 5.3 µW and approximately 3,000-fold power margin were incorrect. The ADC node is 0.9046 V. The 10 nF reservoir C4 is now beside the ADC pad; the divider/filter time constant is approximately 0.678 ms. Choose calibrated attenuation with enough input range to detect an overvoltage above nominal, rather than clipping near 400 V.

All three anode-ballast nodes sit near 400 V when the tube is idle. Under sustained conduction, the 4.5 MΩ string bounds current to approximately 89 µA before accounting for the 100 kΩ cathode resistor; each 1.5 MΩ resistor sees approximately 133 V at the nominal output. The four 7.5 MΩ divider resistors each drop about 100 V. These are separate component working-voltage checks, not permission to route the intermediate anode nodes as low voltage.

The 100 kΩ / 47 pF pulse network and BAT54S rail clamp remain. U2 pin 1 is COUNT, 2 GND, 3 pulse input, 4 threshold, and 5 3V3. The threshold divider is approximately 0.511 V; the 1 MΩ feedback path produces approximately 0.300 V input offset when COUNT is high, below the idle trip threshold. This avoids a DC latched-high state in the nominal resistor model. Pulse shape, noise rejection, clamp current, false counts and actual hysteresis still require a prototype. Pin mapping follows the [TLV3201 datasheet](https://www.ti.com/lit/ds/symlink/tlv3201.pdf).

The GNSS DDC interface has internal pull-ups, but external resistors can be necessary for 400 kbit/s; see the [MAX-M10S datasheet](https://content.u-blox.com/sites/default/files/MAX-M10S_DataSheet_UBX-20035208.pdf). RPU1/RPU2 supply explicit 4.7 kΩ pull-ups. Start at 100 kHz; qualify rise time before 400 kHz. VCC_RF, RANT, L2 and the antenna must be checked together for bias current and RF loss. The choke is close to its specified self-resonant region at GNSS L1; its nominal inductance alone does not prove the installed bias tee.

### Converter simulation: useful evidence, limited scope

`simulation/boost-envelope.cir` uses an ideal controlled switch, a lumped 1 mH coil with 1.7 Ω winding resistance and assumed winding/collector capacitance, a generic ultrafast diode approximation, and an approximate negative collector clamp. These are **not manufacturer transistor/diode switching models**. The run uses 5 kHz, 70 µs maximum pulses and ideal 395/405 V cycle-skipping feedback. In the saved run, output averages approximately 400 V, ranges about 394–415 V, collector peak is about 426 V and coil peak about 215 mA. An earlier 20 kHz / 23 µs case could not reach 400 V after the negative collector clamp was represented.

This establishes an idealized feasibility envelope only. It does not validate GPIO drive strength, BJT storage time, safe operating area, winding insulation at the actual flyback voltage, hot diode leakage, layout capacitance, regulation timing or fault behavior. Do not transplant those model settings into continuously running firmware. The [ESP32-S3 datasheet](https://documentation.espressif.com/esp32_s3_datasheet_en.pdf) specifies drive-dependent GPIO characteristics; verify the configured drive and actual pin voltage under the pulsed base load.

## Footprints and assembly review

| Group | Reviewed disposition |
|---|---|
| MOD1 | Corrected XIAO pad coordinates and pad sizes preserved exactly against the original board; USB faces left, supply pins toward U1. No new castellated via-in-pad. |
| U1 / J1 | Native u-blox MAX and Hirose U.FL footprints retained; numbered pad nets checked. GNSS is at the upper left; RF path stays on the front copper with no signal vias. |
| C2 / C3 | [TDK CGA6M](https://product.tdk.com/en/search/capacitor/ceramic/mlcc/info?part_no=CGA6M1C0G3A472G200AC): body 3.2 × 2.5 × 2.0 mm; local footprint uses 1.1 × 2.2 mm lands, 3.3 mm center spacing and 2.2 mm gap. |
| ESD1 | [TI DPY package](https://www.ti.com/lit/gpn/tpd1e0b04): 0.3 × 0.5 mm lands on 0.7 mm pitch. Bidirectional TVS, two pads. |
| L2 | [Murata LQG15HS](https://www.murata.com/en-us/products/productdetail?partno=LQG15HS27NJ02%23): 1.0 × 0.5 mm body, native 0402 footprint. |
| Q1 | SOT223 with collector tab on pad 2; pin map independently checked. |
| D1 / D2 | Purchased Vishay US1M-E3/61T, SMA/DO-214AC; pad 1 cathode, pad 2 anode. [Manufacturer specification](https://www.vishay.com/docs/88758/us1.pdf). |
| D3 | BAT54SLT1G, SOT23; pad 1 GND, 2 3V3, 3 pulse. [Manufacturer specification](https://www.onsemi.com/download/data-sheet/pdf/bat54slt1-d.pdf). |
| U2 | TLV3201AIDBVT, five-pad DBV/SOT23 footprint; schematic uses a compatible generic pin drawing with the actual part value. |
| L1 | [Bourns SRR1260](https://www.bourns.com/docs/product-datasheets/srr1260.pdf) footprint retained, rotated to face its switch pad toward Q1. 12.5 mm body dominates board area and height. Winding voltage and saturation behavior need operating-point qualification. |
| Resistors | 1206 retained for all seven 200 V working-rated HV resistors; 0603 for low-voltage resistors. Resistor voltage, rather than dissipation alone, governs the HV strings. |
| Other capacitors | Purchased website substitutions retained: 0603 C1/C4/C5/C6/C7/C9 and 1206 C8. Their supply-voltage ratings exceed the applied nominal low-voltage rails. |
| J2 / R5 / R6 | JST-SH side entry, opening toward lower edge. Pin 1 GND, 2 TX, 3 RX; 100 Ω series resistors. Mount pads are not signal pins. |
| MC1 / MC2 / H1–H3 | Plated contact solder holes and three unplated enclosure mounting holes; washer exclusions persist as native all-copper-layer rule areas. |

The website's SOT23/SOT223 bodies, diode polarity stripe, test pads and contact solder holes now follow the reviewed geometry. The corrected tube and direct spring-clip models are assembly aids; copper and drill files are authoritative for fabrication.

## Checklist disposition

| Rule | Change / verification |
|---|---|
| 11 — unfilled via-in-pad | Independent drill-to-SMD-land audit finds none. Ordinary through vias; no filled/capped-via process required. |
| 10 — test access | 17 front-side 1.5 mm probe pads, including both ground returns, 3V3, VBUS, RX, PWM and antenna supply. TP1 moved clear of the provisional tube end. Pad locations are in `testpoints.csv`. |
| 9 — thermal paths | Larger Q1 collector land and ordinary local copper; deliberately limited collector area to avoid added switch-node capacitance. Component temperatures and switching loss remain a bench gate. |
| 8 — edge spacing | Four-layer outer reference distance is 0.2104 mm, rather than the full 1.6 mm board thickness. RF and fast logic are kept in the low-voltage area; connector escapes terminate at their connectors. No USB differential routing exists on this carrier. |
| 7 — stitching | Ground stitching surrounds the low-voltage/RF area, with additional local returns and checked parallel supply vias where space permits. See `return-vias.json`. |
| 6 — switching loops | SW, PUMP and HV+ routes remain on F.Cu with no signal vias. L1 faces Q1; C8/C9 moved to L1's supply side, reducing C8-to-L1 pad distance from 18.35 mm to approximately 2.68 mm. Ground returns use local copper and vias. The large purchased coil limits loop compactness; measure EMI and GNSS desense. |
| 5 — differential pairs | Not applicable to carrier copper: USB and the ESP32 RF feed reside on the XIAO. GNSS is single-ended 50 Ω RF; I²C and UART are single-ended logic. |
| 4 — power routes / vias | 0.4 mm power and switch routes, 0.5 mm HV routes, and checked parallel supply vias where possible. Local decoupling handles switching current; one via's presence is not a rail-current qualification. |
| 3 — antenna copper | External antennas are required. Do not put an antenna element over this carrier or its metal enclosure. GNSS U.FL has local ground; the XIAO antenna must be positioned according to Seeed's guidance. Copper pours are removed under the provisional tube envelope. |
| 2 — decoupling | Pad-center distances: C4–ADC 2.21 mm, C5–U2 2.59 mm, C6–U1 2.48/2.71 mm. C8 at L1 input and C9 beside it. These are geometric distances; trace continuity and return paths were also checked. |
| 1 — plane splits | Added In1.Cu/In2.Cu ground references beneath the low-voltage region. Independent 0.2 mm sampling of RF, count, PWM, I²C and UART routes finds no plane gaps away from their own via antipads. Ground is omitted below the HV region to limit parasitic coupling. |

This is a rule-by-rule engineering disposition, **not a claim of passed EMC testing**. The checklist's thermal, RF and EMI outcomes need measurements.

### High-voltage spacing

Persisted project rules use 2.8 mm between approximately 400 V nets and low-voltage copper, including zones; intermediate divider rules use 2.8 / 1.5 / 0.8 mm. SW and PUMP are also checked against charged DC nodes because they fall near zero during switching. Inter-HV pairs have explicit 0.8 / 1.5 / 2.8 mm checks using the larger voltage difference at idle or nominal sustained tube conduction. Rated component lands and immediate escapes have documented exceptions for Q1, C2/C3 and D1/D2. These package exceptions exclude zones and foreign nets; do not use them to route unrelated traces through those courtyards. Native rule areas clear all layers around mounting hardware.

These are project PCB clearances for a clean, dry, enclosed prototype, not a mains or reinforced-insulation certification. Clean flux residues, especially around the high-impedance divider. The design has exposed HV test pads and needs an insulating enclosure.

### Stack and RF

Four layers, nominal 1.6 mm FR4, ENIG, 35 µm outer and 15.2 µm inner copper. The native stack follows [JLC04161H-7628](https://jlcpcb.com/impedance): 0.2104 mm outer dielectrics and 1.065 mm core. The RF trunk is 0.36 mm with 0.20 mm coplanar gap and short 0.20 mm pad necks. The saved quasi-static estimate is **50.95 Ω**, excluding solder mask, finite ground, pads and connector discontinuities; equations are documented by [Qucs](https://qucs.sourceforge.net/tech/node86.html). Request 50 Ω ±10% control on the RF trunk and review the fabricator's stack/width response. Do not substitute an arbitrary four-layer stack or order two layers.

## Tube orientation and direct spring clips

Closed metal can = K(−) → GM_CATHODE; isolated pin = A(+) → GM_ANODE. Default: can at MC1, pin at MC2, JP1 links 1-3/2-4. Reversed: swap contacts and fit 1-2/3-4. Selected pair: Littelfuse 01000058Z and Keystone 6049. PocketMagic nominal dimensions are 16 × 6 mm body, 5 × 2 mm pin, 21 mm overall. The earlier factory 2.01–2.15 mm pin envelope remains a socket-fit gate.

MC1/MC2 have identical four-hole plated patterns, duplicate pad 1 on TUBE_LEFT/TUBE_RIGHT. JP1 selects the electrode mapping; both site nets receive 2.8 mm clearance to other nets. H4/H5 and the screw hardware are removed. The updated routing clears the new packages; Ballast parts, RANT and TP1 move locally. The tube is removable and requires no flying leads.

See [tube-mount-research.md](tube-mount-research.md) and [tube-mount-bom.csv](tube-mount-bom.csv). The 3.5 mm tube axis and 0.325 mm socket stand-off are provisional. Sample grip, end stops, actual pin acceptance, engagement, seat height and three-dimensional HV insulation remain open. A clean PCB DRC does not qualify clearance between the installed can and the anode socket or its solder joints.

## Commissioning and remaining release gates

1. Inspect soldering, polarity, Q1 pinout, tube wiring and shorts with power disconnected. Leave the tube disconnected for converter qualification. Fit the replacement transistor and resistors; do not fit the purchased MMBTA42 in the revised position.
2. Begin with PWM disabled and a current-limited source. Check VBUS, 3V3, GPIO reset state, UART and GNSS first. J2 is 3.3 V logic only, with crossed TX/RX and common ground; it does not carry power.
3. Use bounded, finite HV pulse bursts. Measure collector voltage with a suitably voltage-rated, low-capacitance probe and a short ground connection at GND only. Probe attenuation alone does not establish a voltage rating. Never put an earth-referenced scope ground clip on TP1, TP5 or TP8. Probe capacitance can substantially change this converter.
4. Establish a safe pulse envelope from measured current, peak voltage, device temperature, output rise and leakage. Stop for unexpected current, inadequate output rise or excessive overshoot. A 480 V collector commissioning ceiling provides a provisional 20% margin below Q1's 600 V absolute maximum; it is not a substitute for a switching SOA assessment. Implement calibrated ADC overvoltage detection, stale-feedback timeout, reset shutdown and watchdog behavior before continuous operation. This board has **no independent hardware overvoltage cutoff**.
5. Qualify regulation, ripple, startup, shutdown, open tube and abnormal feedback behavior over the intended supply/temperature range. The nominal discharge time constant through the divider is 141 ms; do not rely on a timer alone. Disconnect all power and verify TP8 below 5 V with a rated meter before handling.
6. Measure the actual tube before selecting retention hardware. Check plateau/count response and comparator behavior with the converter active. Check GNSS acquisition and signal quality with HV off/on, I²C rise time, antenna current, thermal behavior and enclosure clearance. A subsequent hardware revision may be needed if these tests fail.

**Production/wearable release remains withheld until those measurements and fault-control checks are complete.** A clean bare-board fabrication package is not evidence that the assembled 400 V circuit is ready to wear or use as a calibrated dose instrument.